1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to a ferroelectric random access memory device and a control method thereof, to provide a stabilized write operation.
2. Discussion of the Related Art
To overcome the refresh limit necessary for a large capacity DRAM (Dynamic Random Access Memory), a ferroelectric thin layer is applied to a dielectric layer of a capacitor. A ferroelectric Random Access Memory (FRAM), using such a ferroelectric thin layer, is a kind of nonvolatile memory device that has the advantage of remembering storage information even when there is a power loss, operates at a high-speed and at reduced power consumption reduction. Such a ferroelectric memory is expected to be used as a main memory device or a record medium to record sound or image, in various electronic instruments and equipments having file storage and detection functions such as portable computer, cellular phone and game machines etc.
In such a ferroelectric RAM device, a memory cell is constructed of a ferroelectric capacitor and an access transistor, which store logic data ‘1’ or ‘0’ in conformity with an electric polarization state of a ferroelectric capacitor.
FIG. 1 illustrates a general hysteresis curve for ferroelectric material constituting a ferroelectric memory cell. The curve assumes that between the two electrodes of the ferroelectric capacitor a voltage is applied to the ferroelectric material, wherein the electrode of the capacitor connected to a plate line is the positive electrode, and the other, the negative electrode; in the hysteresis curve the X axis indicates the voltage applied to both ends of the capacitor, and the Y axis indicates the quantity of charge excited to the surface by a spontaneous polarization of the ferroelectric material, that is, a polarization (μC/cm2).
Referring to FIG. 1, if a ground voltage Vss or 0V is applied and no electric field is applied to the ferroelectric material, a polarization is not generated. When the voltage across both ends of the ferroelectric capacitor increases in a plus direction, a polarization or charge quantity increases from zero to a state point A within the positive polarization region. At the state point A a polarization is generated to one direction, and a polarization of the state point A becomes a maximum value. At this time, a polarization, namely a charge quantity, is kept in the ferroelectric material, and is marked as +Qs. After that, even if the voltage across both ends of the capacitor falls to the ground voltage Vss, the polarization is not lowered to zero but remains at a state point B. For this residual polarization, the charge volume kept in the ferroelectric material is represented as +Qr. Next, if the voltage across both ends of the capacitor increases in a minus direction, the polarization is changed from a state point B to a state point C, within the negative charge polarization region. At the state point C, ferroelectric material is polarized to a direction opposite to the polarization direction of the state point A. This polarization is represented as −Qs. Then, even if the voltage across both ends of the capacitor again falls to a ground voltage Vss, the polarization does not fall to zero but remains at a state point D. This residual polarization is represented as −Qr. When the voltage applied across both ends of the capacitor again increases to a plus direction, the polarization of the ferroelectric material is changed from the state point D to the state point A.
As above, if a voltage for generating an electric field is applied once to a ferroelectric capacitor, where ferroelectric material is inserted between the two electrodes, a polarization direction based on spontaneous polarization is maintained even if the electrodes are in a floating state. The surface charge of ferroelectric material, through the spontaneous polarization, is not naturally lost by leakage etc. If a voltage is not applied in an opposite direction so that a polarization becomes zero, the polarization direction is maintained intact.
When a voltage is applied in a plus direction to the ferroelectric capacitor and is then removed, The residual polarization of the ferroelectric material constituting the ferroelectric capacitor becomes a +Qr state. When a voltage is applied in a minus direction to the ferroelectric capacitor and is then removed, the residual polarization of the ferroelectric material becomes a −Qr state. Here, if assuming that a logic state at the +Qr state of residual polarization indicates data ‘0’, the logic state at the −Qr state of residual polarization indicates data ‘1’.
FIG. 2 illustrates memory cells constituting a memory cell array of a conventional ferroelectric RAM device. A memory cell is constructed from one access transistor N1 and one ferroelectric capacitor C1. The access transistor N1 includes two terminals, a source and a drain, connected between one electrode of the ferroelectric capacitor C1 and a bit line B/L. The gate of the access transistor N1 is connected to a word line W/L. Another electrode of the ferroelectric capacitor C1 is connected to a plate line P/L.
A plurality of memory cells is arranged into rows and columns, constituting a cell array. Read and write operations in such a ferroelectric RAM device are performed by controlling pulses that are applied to the ferroelectric memory cell.
To guarantee a stabilized write operation in such a ferroelectric RAM device, the time to write respective data should be ensured. Thus, a section to write data ‘0’ and a section to write data ‘1’ are each determined to exist separately within one cycle. Mainly, the section to write data ‘0’ is first determined and then the section to write data ‘1’ is determined. Particularly, in a ferroelectric RAM device having an asynchronous operation, one cycle operation is controlled by an address transition detection (ATD) signal, so as to perform a write operation.
FIG. 3 illustrates a timing diagram for the operation of a ferroelectric RAM device according to the prior art. Here an external chip enable signal CEB maintains a low level when in an enable state, and in this state an address signal XADD is applied from the outside. A transition of the address signal is sensed, generating the address transition detection signal ATD, and an internal chip enable signal ICE is generated by the address transition detection signal ATD. When the ICE is generated, a word line W/L is enabled by a word line decoder and driver circuit. Also, a plate line P/L is enabled in response to the ICE. When the plate line P/L is enabled, a read section I starts on operation. A voltage corresponding to data stored in a memory cell is excited to a bit line B/L maintaining a ground voltage state. Next, a sense amplifier enable signal SAP is generated, in response to the enable signal of the plate line, to enable a sense amplifier. When the sense amplifier is enabled, the read section I is completed. The next section is write section II for writing data ‘0’. In this section when the data signal DATA is later inputted from the outside, the signal DATA is excited to the bit line B/L. If the data excited to the bit line B/L is ‘0’, the voltage of the bit line maintains a ground voltage state. Thus, data ‘0’ is written by a voltage difference between plate line P/L (having an enable state) and the bit line B/L (having a ground voltage state). Meanwhile, if the data excited to the bit line B/L is ‘1’, the voltage of the bit line maintains a power source voltage state; thus, since there is no voltage difference between the plate line P/L (having an enabled state) and the bit line B/L, nothing is generated. The write operation of the data ‘0’ is performed before the plate line P/L is disabled, which occurs after the generation of the sense amplifier enable signal once a given time has lapsed. The subsequent section, between the plate line P/L being disabled and the sense amplifier being disabled, is provided as a write section III for writing data ‘1’. In this section when the voltage of the bit line B/L has a power source voltage level, by virtue of the voltage corresponding to data ‘1’ excited to the bit line B/L, and the plate line P/L maintains a disable sate the data ‘1’ is stored at a memory cell by the voltage difference between the bit line B/L and the plate line P/L. When the write operation is completed, the bit line B/L is precharged and the signal ICE is disabled.
In the conventional ferroelectric RAM device when performing such a write operation, a plate line P/L is enabled and after a lapse of time corresponding to the read section I, a sense amplifier is enabled. After the enabling of the sense amplifier, time lapses corresponding to the write section II for writing data ‘0’, and then the plate line P/L is disabled. After the disabling of the plate line P/L, time corresponding to the write section III for writing data ‘1’ lapses and then the sense amplifier is disabled.
In the conventional ferroelectric RAM device, read and write cycle time is mainly decided by these sections. When the respective sections become equal to one another by a given time, there are advantages of reducing a cycle time and having the same cycle time, thereby simplifying a control operation of ferroelectric memory. However, data to be written in a memory cell should be inputted within the write section II of data ‘0’ at least. If the data is inputted later or if there is not enough time for writing data, even if inputted within the write section II of the data ‘0’, a failure will occur since the data cannot be stored in the memory cell.
FIG. 4 is a timing diagram illustrating write operations in a ferroelectric RAM device having a long cycle according to the prior art, where the operation of the ferroelectric RAM device is similar to FIG. 3. However, in the case of a write operation during the long cycle, the probability of a failure occurring is higher than that of the ferroelectric RAM device having a short cycle similar to FIG. 3. For example, data may be inputted after the write section II for writing data ‘0’ or after the write section III for writing data ‘1’. In this case, the inputted data cannot be written or undesired data is written in the memory cell, causing a failure.
FIGS. 5 and 6 are timing diagrams illustrating write operations in a conventional ferroelectric RAM device attempting to overcome problems depicted in FIG. 4.
FIG. 5 depicts a timing diagram illustrating the operation of a conventional ferroelectric RAM device to ensure a write section by disabling a plate line P/L in response to an address transition detections signal ATD of the next cycle. The read section I, in which the plate line P/L is enabled and the sense amplifier is enabled, is the same or similar to the operation depicted in FIG. 4. Meanwhile, the write section II for writing data ‘0’ starts on an operation when the sense amplifier is enabled, and becomes continuous till the plate line P/L is disabled by the ATD generated by sensing the address signal of the next cycle, instead of disabling the plate line P/L after the sense amplifier is enabled and then a given time lapses. Within this write section II of the data ‘0’, the write section of the actual data ‘0’ is a section that starts from the time of a data input to the disabling time of the plate line. The lapse of time occurring after the disabling of the plate line P/L corresponds to the write section III of data ‘1’, after which the sense amplifier is disabled, and the write section III of the data ‘1’ exists within the next cycle.
FIG. 6 is a timing diagram for operations of a conventional ferroelectric RAM device to ensure a write section by independently enabling a plate line P/L through use of a write enable signal WEB. The read section I, in which the plate line P/L is enabled and the sense amplifier is enabled, is equivalent to the operation of FIG. 4. That is, after the plate line P/L is enabled and the time corresponding to the read section I lapses, a sense amplifier is enabled. After the enabling of the sense amplifier and the subsequent lapse of a given time, the plate line P/L is disabled. At this section, the plate line P/L is again enabled independently by an applied write enable signal WEB, regardless of the state, disabled or enabled, of the plate line P/L. The plate line P/L consecutively maintains an enable state till the plate line P/L is disabled by an address transition detection signal ATD, generated by sensing the address signal of the next cycle. Thus, the section where the sense amplifier is enabled and then the plate line P/L is disabled by the address transition detection signal, becomes the write section II of data ‘0’. Within this write section II of the data ‘0’, a write operation of the actual data ‘0’ is performed from the time when the data signal DATA is applied. After the disabling of the plate line P/L and a subsequent lapse of time corresponding to the write section III of data ‘1’, the sense amplifier is disabled, and the write section III of the data ‘1’ exists within a next cycle.
In the ferroelectric RAM devices shown in FIGS. 5 and 6, the enable section of plate line is prolonged, thus the write section II of the data ‘0’ can be prolonged as well. This provides a stabilized write operation of data ‘0’ even if an input of data comes late. In this system, however, the write section of data ‘1’ is pushed into the next cycle by as much as the write section of data ‘0’ is prolonged, thus the write cycle time increases and cycle times of read operation and write operation become different. The write section of data ‘1’ exists in the next cycle, thus also increasing the read or write operation cycle the next applied address signal. In controlling such a ferroelectric RAM device mutually different cycle times should be applied in conformity with a cycle and cycle configuration, thus a control of the ferroelectric RAM device becomes complicated. In this case the longest cycle is equally applied to all cycle times to solve such a control complication, thus there is a disadvantage in the speed aspect of the device.